This invention relates generally to computer systems, and more particularly to register files for use in computer systems.
In general, computer systems employ registers to store data. Register files (a collection of registers), in general, are multi-ported memory elements that fall in the performance critical path of general-purpose microprocessors. The demand of having high-speed multi-ported reads and writes generally forces the designer to use dynamic circuit techniques to design high performance register files.
FIG. 1 is an example of a general architecture of a dynamic register file array. The array is broken down into groups, each group typically containing 16 words. As can be seen from FIG. 1, this particular register array has two groups, each containing 16 words, and each word consisting of 32 bits. In operation, the clock delineates the precharge phase and the evaluation phase of the register file array. During the precharge phase, each of the local bitlines is precharged. During the evaluation phase, one of the read select lines is asserted to indicate which of the 32 words in the array is to be evaluated.
Thus, the outputs of each of the data cells in a group are multiplexed together in a dynamic multiplexer to form a local bitline. The local bitlines are then combined and drive a second dynamic multiplexer stage to generate the global bitline signals.
The number of words that can be grouped together is limited by the robustness of the particular register file array. Robustness is a measure of the register file""s ability to handle noise such as leakage of current from the local bitline during the evaluation phase. Leakage occurs when current discharges from the local bitline through the n-type metal oxide semiconductor (xe2x80x9cNMOSxe2x80x9d) transistors located in each cell. Leakage is undesirable since it can result in incorrect evaluations if too much current bleeds off of the local bitline during the evaluation phase. In general, a target robustness of 0.14 (e.g., robustness=direct current unity gain noise margin/Vsupply voltage) is desired.
In addition, it is desirable to minimize read delay of the register file. Read delay is the time from which the read select for the particular word to be evaluated is asserted until the result is output to the global bitline. However, there is usually a tradeoff between speed and robustness.
For example, if two low threshold voltage transistors are used to discharge the local bitline, the read delay is acceptable, but such an implementation results in 0.0 robustness. In another implementation, two transistors are used (known as dual threshold voltage) to discharge the local bitline, one of the transistors (usually the read select transistor) has a high threshold voltage and the other one (usually the one coupled to the data cell) has a low threshold voltage. In such an implementation, the read delay is 10 percent greater than the read delay of a low threshold voltage implementation, and the robustness is increased to 0.09, which still fails the robustness test. Therefore, both of these implementations fail to achieve the desired robustness of 0.14.
In order to achieve the desired robustness, the dual threshold voltage implementation has been used along with an upsized dynamic keeper, which is circuitry which dynamically holds the local bitline in a precharged condition despite leakage through the pull down transistors. Such an implementation achieves the desired robustness, but the upsized keeper increases the register file read delay to a point which is 24 percent greater than the low threshold voltage implementation, which is much too slow. Furthermore, the dynamic keeper is controlled by the output of the local bitline, which can change state due to noise or leakage. Thus, if the local bitline changes state, the condition is non-recoverable in that the dynamic keeper cannot revert the local bitline output back to the original state.
Moreover, the previously described implementation of register file arrays all use clocks to delineate the precharge and evaluation phases of the register file array. Thus, each local bitline precharge transistor is continually switched regardless of whether the word to be evaluated is located in the particular group to which the local bitline is connected.